FPGA, The Next Wave of HFT Technology?
Thu, 30 Jun 2011 07:19:00 GMT
At a trade conference recently, the platform asked for a straw poll of those people developing solutions using FPGA (Field Programmable Gate Arrays), about a third of the room put their hands up. This is a new technology to the financial services industry and is beginning to be adopted into the HFT stack and I thought it was worth finding out what the buzz is all about.
Gate arrays have in fact been around since the beginning of the digital revolution and consist of rows of logic gates, AND, XOR and the like. FPGAs areprogrammable from their ability to wire up the gates to perform complex logical operations; the field part comes about because they are customer programmable, after manufacture. Comparing them to the CPUs of Intel or AMD is like comparing an insect brain to a human brain. The brain of a bee has to take a small number of inputs and take a decision; is it warm, is it light, is it raining; then leave the hive to forage for nectar. In terms of logic, if A AND B, NOT C, answer X. However, bees don’t have art or culture which those blessed with more sophisticated brains can achieve, but we recognise bees achieve remarkable feats of hive construction, navigation and honey production with very little brain power. FPGAs have very little digital brain power but smart people can do remarkable things with them.
Using a device to do a relatively simple task consistently, without interrupts or other distractions, has some attraction for those who are trading 1000s of times a second for two reasons, jitter and reliability. The jitter issue is caused by our complex CPUs running generic operating systems that have complex schedulers to ensure that keyboards get read, monitors get refreshed, network packets get acknowledged and yes, the trading algorithm gets run. The FPGA runs just one programme, the one that is literally wired into the array. The level of sophistication of the programme that can be deployed depends on the number of gates in a row, the number of rows and the use of memory blocks or full random access memory (RAM). Time and effort also have a big impact on the sophistication of the FPGA programme. A simple threshold trading programme that monitors the price and a stock and pulls a trigger when a particular value is reached, can be quite easy to deliver in a month or two. Something that performs an execution risk calculation in the trade flow would take a couple of man years to work to implement. Hobby projects to get the kids interested in gate arrays can be found here. As I said, FPGAs have been around for a long time and are often used in education as an introduction to electronics.
Why FPGA in HFT?
This venerable technology has one advantage–it is fast! It takes one clock cycle to do the calculation. Taking a risk calculation that takes 30 microseconds on a general CPU down to 3 microseconds is quite feasible, and in the world of sub millisecond trading, that matters. You could think of it as a microsecond budget, the investment decision is reduced to a simple spreadsheet exercise. Adding to the challenge is the regulatory influence post “flash crash” that requires firms to undertake a risk calculation in the trade flow.
Getting close to the wire
Combining FPGA with network cards allows programs to be run without the need to send data across the computer to the CPUS. The programming space on the array is limited, so the programs can’t be too big, but the advantage of a simple threshold trigger is obvious, particularly when considering the “circuit breaker” design concept that has evolved post “flash crash.” “If the trading goes out of bounds stop trading,” is the kind of algorithm that’s a good example of the application of FPGAs in HFT.
Getting close to ASICs
The more sophisticated the program, the closer the design comes to the world of signal processing and a whole slew of technologies that would not normally be considered in the finance sector. The advantage of the programmable array is that it is easy to prototype and a change is no more complicated than a firmware update. The next technological step would be to design an ASIC (Application Specific Integrated Circuit) to do the job. The hitch is the cost to produce the first ASIC–a million dollars, the second costs hardly anything, but the ROI is more palatable for a FPGA. I can imagine some of the software houses that have developed the market data and trade execution applications looking to FPGA technology as nothing more complicated than a different deployment platform and a stepping stone to ASIC design. However, moving into the FPGA will take software designers into a new and possibly uncomfortable place, electronics engineering and signal processing.
So what does it cost?
Where to begin?
A good start is to look at the existing HFT infrastructure, is there an optimisation program that would take the firm just ahead? In the trading game there are no prizes for world records, being just ahead of the competition is all that is required to trade successfully. Looking into the network, replacing the standard network switches and cards with low latency devices is a great start. Tuning the kernel and BIOS settings of the server will reduce jitter. Switching off power save mode of the server may not be green but will ensure the CPUs are fully spun up and ready to trade. Check that code for latency traps and replace all logging and journal devices with IO optimised solid state storage. Those housekeeping tasks can be done in parallel with a development cycle that includes FPGA.
These four leading FPGA manufacturers each have high performance and low cost solutions–Actel’s igloo range is also low power, ideal for battery powered mobile devices:
The gate array itself is implemented on a PCB (printed circuit board) and there are numerous manufactures who also provide development software and starter kits. The following site lists a board range:
…but isn’t exhaustive and may not be up to date. For instance, Fiberblaze isn’t listed, but they have been advertising at HFT events a card with two 10GE Ethernet ports and the Virtix 5 FPGA from Xilinx.
Once you have purchased the board, you will need to download and install the FPGA design software onto your workstation. Enter a design, compile it, download to the board and watch it run. Starter kits begin at $100, but I chose the Diligent Spartan 3E Starter board ($189) because it had Ethernet connectivity and was fully compatible with the Xilinx free WebPack software.
By completing a couple of tutorials (there are plenty online), you will build your confidence and be ready for the steep learning curve, Hardware Definition Language (HDL). HDL comes in two flavours , “VHDL”, which is strongly typed like PASCAL and “Verlilog”, weakly typed like ‘C’ both cover the three main subjects.
Ports and signal declaration
Assignments and processes
To fully master the language and provide the level of sophistication and confidence to deploy into production will take months of learning, testing and discussion with peers.
Will FPGA ever catch on in HFT?
There is a niche for this technology but it is not capable of taking the whole complex HFT stack and putting it on an array. Based on the straw poll, it is drawing attention and has its place in medium to large HFT design shops. Some software houses are placing bets on the need for in-flow risk calculation such as Ullink’s Iris+and Fixnetix’s iX-ecute, which provide filtering based on user defined parameters and prevent execution risk related orders. I suspect that more generally FPGA will be hidden to most users and described as “hardware circuit breakers” or “inline filtering” wrapped in a trader friendly management interface that sets threshold parameters and generates alerts and reports that completely obscure the underlying gate array.
I doubt that many folks will implement FPGAs themselves, but the technology will be used extensively by the sell-side and exchanges to satisfy post “flash crash” filtering concerns. In time I expect these filters will be implemented in ASICs by a relatively few designers who will sell them to low latency network card producers, just as firewall software, also sophisticated filtering, is now being implemented as ASICs for the low latency market.
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David Quarrell has more than two decades’ experience implementing technology solutions, 15 of which have been in service to the financial sector. Prior to joining Agilysys Technology Solutions in the United Kingdom as senior solutions architect and technology consultant, he was principal engineer and lead consultant for Sun Microsystems, London. Having been educated at Coventry University in Electronic Engineering, David’s transition to computer science was a natural progression. Certification as a Java SCEA Solution Architect further enhanced his industry standing, leading to participation in large-scale benchmarking and performance-tuning exercises for Sun’s largest IT projects.
David has played a major role in the automation of transaction, settlement and electronic exchanges, where he has the dual distinctions of configuring the systems that replaced the LIFFE open outcry market and building the surveillance systems for the London Stock Exchange. His ability to exploit technology and understand the non-functional requirements of a business has been key to operational excellence and success. Goal-driven and a creative problem solver, he addresses complex challenges and delivers results against demanding timescales, taking into account commercial, operational, strategic and technical requirements. Of late, David’s expertise in low-latency networking, performance and security has been in particular demand, having been inspired by the prominence of high-frequency trading, or “trading where speed matters,” in the U.S. and European markets. With today’s need for split-second execution, HFT continues to gain market share of daily trades.
In his spare time, David is a die-hard Welsh rugby fan, and also enjoys when warm weather arrives so that he may spend days hill walking in Scotland and indulging his passion for sailing. He has skippered a 10m (33-ft) sailing yacht for a number of years and often provides needed support to host regattas in the sport he enjoys so much. He shares his views on his blog: www.AgilysysFinancialITBlog.com
If you would like to reach David, please contact Anita O’Malley at +1 732.692.1934